SV18. A Deep Dive into OBI: Building Your First Master and Slave Controllers
In this tutorial, we'll demystify OBI by designing and verifying a minimal master from the ground up.
SV17. FIFO Design and Implementation
A First-In-First-Out (FIFO) buffer is a fundamental digital design component that stores data in a queue-like structure. This guide provides a comprehensive explanation of FIFO design principles, depth calculation methods, and a complete SystemVerilog implementation suitable for synthesis.
SV16. Finite State Machines (FSM)
Finite State Machines (FSMs) are fundamental building blocks in digital design, providing a structured approach to implementing sequential logic. This guide covers synthesizable SystemVerilog FSM design techniques, from basic concepts to advanced implementation strategies.
SV15. SystemVerilog Clock-to-Q Modeling: Why Non-Blocking Assignments Matter
This guide focuses on one of the most important timing parameters: Clock-to-Q delay and how to model it effectively in RTL design.
SV14. Unique and Priority Identifiers in SystemVerilog
SystemVerilog provides three special keywords (`unique`, `unique0`, and `priority`) that can be used with `case` and `if` statements to provide synthesis tools with optimization hints and enable runtime checking during simulation.